drivers: espi: microchip: xec: Port version 2 eSPI to MEC174x/5x#105308
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scottwcpg wants to merge 5 commits intozephyrproject-rtos:mainfrom
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drivers: espi: microchip: xec: Port version 2 eSPI to MEC174x/5x#105308scottwcpg wants to merge 5 commits intozephyrproject-rtos:mainfrom
scottwcpg wants to merge 5 commits intozephyrproject-rtos:mainfrom
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Customer demand requires porting the MEC172x version 2 eSPI driver to MEC174x/5x/165x. We must move the eSPI V2 headers out of the MEC172x SoC directory into a common directory. There are several other small changes due to register differences in various hardware subystems such as PCR, KBC-8042, QMSPI, etc. Signed-off-by: scott worley <scott.worley@microchip.com>
Microchip XEC V2 eSPI hardware changes Host address BARs. Host address bits [47:32] are now common to all peripheral channel device memory BARs and the SRAM BARs. Two registers contain these upper address bits. We add optional device tree properties to specify these values. If not present bits [47:32] of host address in all BARs are 0. Signed-off-by: scott worley <scott.worley@microchip.com>
We standardize the eSPI V2 driver device tree properties for MEC172x, MEC174x, MEC175x, and MEC165xB. Signed-off-by: scott worley <scott.worley@microchip.com>
This part of the porting eSPI V2 driver which includes ISRs for aggregated GIRQs 24 and 25. By disabling the girq24 and girq25 nodes we prevent the MEC172x interrupt driver from connecting ISRs to these GIRQs. New SoC's do not have an interrupt driver because the ECIA GIRQs are not a true second level interrupt controller. Instead we will use SoC EICA helper functions to program the GIRQ enables. The long term goal is to use SoC helpers for all GIRQ functions and remove the interrupt controller driver for ECIA GIRQs. Signed-off-by: scott worley <scott.worley@microchip.com>
Final commit in the series of porting the legacy eSPI version 2 driver
to MEC174x/5x/165xB. These commits are due to customer demand only.
The eSPI creator, Intel has a proposal for a new eSPI driver where
the eSPI driver is a transport layer for events and data. The application
will handle all interpretation of command and data. We expect a clean,
from scratch implementation of the new driver architecture not based
on this driver.
This driver has been heavily modified as follows:
1. Try to meet the latest Zephyr coding standards.
2. Break up the massive and unmaintable register structure into smaller
structures based on specific hardware functions.
3. Move VWire IRQ handlers into the driver so any changes to VWire
ordering is more easily handled. We also plan to defeature the GIRQ
interrupt driver since MEC/XEC GIRQ hardwar is not a real interrupt
controller.
4. Add support Microchip MEC/XEC mailbox which is an eSPI peripheral
channel device. We modified the eSPI driver header file as follows:
a. Add a mailbox peripheral to the enum for eSPI peripherals.
b. Add custom Host command opcodes to get/set mailbox data using
ACPI EC for host commands.
c. Add ACPI and private event types for Host sending data, command,
or clearing data written to the Host by the EC (OBE).
d. Add a Microchip XEC vendor specific eSPI header with side-band
API's to access the mailbox.
5. Move Serial-IRQ configuration out of the main part of the driver into
the peripheral channel device initialization routines. Serial-IRQ and
BARs are held in reset by nPLTRST active (low). Once the Host
de-asserts nPLTRST VWire the driver calls functions from a table of
peripheral channel devices.
6. Some peripheral channel devices have Kconfig's specifying the Host I/O
address for accessing the peripheral. For most of these if the Kconfig
is not defined we get the addrees from device tree.
7. A subset of peripheral channel devices can also be mapped to Host
memory space. If a device tree property exists specifying the address
we will program the appropriate memory BAR. Be aware this does allow
both I/O and memory BARs to both be enabled.
Signed-off-by: scott worley <scott.worley@microchip.com>
zephyrbot
added
area: Boards/SoCs
platform: Microchip MEC
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requested review from
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Dino-Li,
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This PR only exists due to customer demand for the MEC172x only version 2 eSPI driver to be ported to newer silicon.
They also demanded more features (more peripheral channel HW supported).
It is an interim driver until the new eSPI driver architecture is finalized.
This PR does not include TAF formerly known as SAF since it is a separate but related driver.
TAF will be in another PR.